Hello, I am looking for some guidance in trying to get a Mirny v1.0 (Board v1.0rc5 with ADF5356) working using the newly updated code from Airwoodix that was recently incorporated into artiq beta.
Firmware has been compiled using the latest artiq version following manual, with updated json defined as shown in https://github.com/m-labs/artiq/pull/1563 (and #1561).
My board is v1.0 so I have set clk_sel = 2 for (MMCX) and refclk=125e6 as it is being clocked from the Kasli (following schematic and documentation here https://github.com/m-labs/artiq/issues/1559).
After flashing the Kasli with the new gateware, I then flashed the mirny with the CPLD code from https://github.com/quartiq/mirny
To test the code, I have used the TestMirny.py example from https://github.com/m-labs/artiq/pull/1530. After power cycling the Kasli this runs with no errors but no output. Resubmitting the experiment a few times and it then starts failing at self.ch.init() with ValueError: MUXOUT not high. The RF Switch on ch0 is working (light goes green) but the red PLL Lock light is always lit (suggesting it is not locking).
Has anyone had success getting this working on a v1.0 with ADF5356? Any suggestions for debugging appreciated. Do I need to explicitly set the state of the CLK_DIV pin on the CPLD for example on the v1.0 boards?