Simulating reset

rrestle

How does one drive a sync statement's default reset signal and successfully simulate it using migen? I don't think the simulator supports it. Whereas I can set any other input, no combination of reset that I have tried (and I have tried default clock domain reset and named clock domains as well as named reset signals) will sustain a reset state.

sb10q

You can use ResetInserter and drive its reset signal from the simulation maybe?

rrestle

Thanks for helping. I hadn't seen ResetInserter in any documentation and just finished investigating it. I performed a dir() to learn its interfaces. Whereas it has a control_name property containing "reset," this is a string and cannot be driven for the purpose of simulation. As far as I can tell, ResetInserter has no Signals objects. I also saw ResetInserter has a transform_fragment_insert method but its signature is not clear to me. I don't how to use it.

How did you learn about ResetInserter? Where is a reference?

sb10q

rrestle How did you learn about ResetInserter?

I wrote the first version of it 🙂

Where is a reference?

There is no/little documentation (pull requests welcome, though the focus is mostly on nMigen), but many designs use it - you can search the code for examples.