Hi, I am trying to run the same test code for the AD9910 on an external 10MHz external clock instead of the internal one. I tried changing the device_dp.py file to clk_ref=1 & refclk=10 000 000, but that does not work. The test source code I am running is :

from artiq.experiment import *
import numpy as np

class DDSTest(EnvExperiment):


def build(self):
        self.setattr_device("core")
        self.setattr_device("urukul0_ch0")
 
@kernel
def run(self):
       self.core.reset()
       self.urukul0_ch0.set_att(0*dB)
       self.urukul0_ch0.init()
       self.urukul0_ch0.sw.on()
       self.urukul0_ch0.set(10*MHz,1.0,1.0)
       delay(3000000*ms)
       self.urukul0_ch0.sw.off()

    Marwanh7 that does not work

    You need to give more details.
    From the error message you had posted on GitHub earlier, the PLL VCO is out of range, and you need to set other parameters of the PLL. See the AD9910 datasheet and the artiq.coredevice.ad9910 manual.


      I am not too sure how to go about adjusting the PLL parameters in my code. In core drivers reference PLL are adjusted in a class artiq.coredevice.ad9910.AD9910

      As for the AD9912, I am trying the same procedure, the code runs with no errors, I am setting the frequency in the code to 10MHz and picking up a 125MHz on the spectrum analyzer. source code
      from artiq.experiment import *
      import numpy as np

      class DDSTest(EnvExperiment):
      """DDS test"""


      def build(self):
    self.setattr_device("core")
    self.setattr_device("urukul1_ch0")
 
    
@kernel
def run(self):
    self.core.reset()
    self.urukul1_ch0.init()
    self.urukul1_ch0.sw.on()
    self.urukul1_ch0.set_att(0*dB)
    self.urukul1_ch0.set(10*MHz,0.0)
    delay(3000000*ms)
    self.urukul1_ch0.sw.off()

        Is there anywhere where I can find example codes at least , I am new to the artiq syntax.

        Marwanh7 As for the AD9912, I am trying the same procedure, the code runs with no errors

        Yes, the PLLs are different on the two chips. For the third time, will you please read the AD datasheets?

          I did read the data sheets and I understand that there are PLL parameters that need to be set up ( did not know it was a different configuration for the 2 chips) . I am asking for the syntax at which I can run these parameters, which is why I am asking for an example code. So for example to set frequency I write it in the @kernel def run() as self.urukul1_ch0.set(10*MHz,0.0). For the PLL parameters it seems to me that I need to create an object, and use import artiq.coredevice.ad9910 as ad9910, not sure. I am intern who is still learning this stuff is all relatively new.

            Also would I have to change the PLL parameters in the device_dp.py file itself for each urukul channel. for example default for ad9910 ch0 is device_db["urukul0_ch0"] = {
            "type": "local",
            "module": "artiq.coredevice.ad9910",
            "class": "AD9910",
            "arguments": {
            "pll_n": 32,
            "chip_select": 4,
            "cpld_device": "urukul0_cpld",
            "sw_device": "ttl_urukul0_sw0"

              I had already tried the links you sent, ran this code:
              from artiq.experiment import *
              import numpy as np
              import artiq.coredevice.ad9910 as ad9910

              class AD9910(EnvExperiment):


              kernel_invariants = {"chip_select", "cpld", "core", "bus",
                     "ftw_per_hz", "io_update_delay", "sysclk_per_mu"}


def __init__(self, dmgr, chip_select=4, cpld_device="urukul0_cpld", sw_device=None,
             pll_n=95, pll_cp=7, pll_vco=5, sync_delay_seed=-1,
             io_update_delay=0, pll_en=1):
      
    def build(self):
        self.setattr_device("core")
        self.setattr_device("urukul0_ch0")
 
@kernel
def run(self):
       self.core.reset()
       self.urukul0_ch0.set_att(0*dB)
       self.urukul0_ch0.init()
       self.urukul0_ch0.sw.on()
       self.urukul0_ch0.set(10*MHz,1.0,1.0)
       delay(3000000*ms)
       self.urukul0_ch0.sw.off()
     [upl-image-preview url=https://forum.m-labs.hk/assets/files/2019-10-11/1570806338-714274-ad9910error.png]

              Do not redefine __init__ for EnvExperiment, at least not incorrectly and without a reason. You only need to define the build and run methods.

              The arguments to AD9910 go into the device database, for example add a line "pll_vco": 5 in the arguments section.

                sb10q

                okay thank you I understand that I have to add the rest of the pll parameters in the argument section into the device database. but in what syntax do add it to my code itself, for example for frequency setting it is in the def run as self.urukul0_ch0.set(10*MHz,1.0,1.0). So would the correct syntax be self.urukul0_ch0.pll_vco(5)

                    Marwanh7

                    So I am basically asking what is the syntax for adding the pll parameters ( arguments) in the def or run methods

                      from artiq.experiment import *
                      import numpy as np
                      import artiq.coredevice.ad9910 as ad9910

                      class DDSTest(EnvExperiment):


                      def build(self):
        self.setattr_device("core")
        self.setattr_device("urukul0_ch0")
 
@kernel
def run(self):
       self.core.reset()
       self.urukul0_ch0.set_att(0*dB)
       self.urukul0_ch0.init()
       self.urukul0_ch0.sw.on()
       self.urukul0_ch0.pll_en=1
       self.urukul0_ch0.pll_n=95
       self.urukul0_ch0.pll_cp=7
       self.urukul0_ch0.pll_vco=5
       self.urukul0_ch0.set(10*MHz,1.0,1.0)
       delay(3000000*ms)
       self.urukul0_ch0.sw.off()


                      Marwanh7 but in what syntax do add it to my code itself, for example for frequency setting it is in the def run as self.urukul0_ch0.set(10*MHz,1.0,1.0). So would the correct syntax be self.urukul0_ch0.pll_vco(5)

                      Nothing. Those PLL settings are only in the device database.

                        Thank you that works, I am not getting any error messages when I run the code, However the signal does not seem to lock to the external 10 MHz external sma clock. I used the following parameters for pll,

                        "pll_n":42,
                        "pll_en":0,
                        "pll_vco":1,
                        "pll_cp":7,

                        Which SMA? Did you also set clk_sel correctly?

                        The ext clk in on the front panel of the urukul module, and I set clk_sel = 1 and refclk=10000000
                        device_db["urukul0_cpld"] = {
                        "type": "local",
                        "module": "artiq.coredevice.urukul",
                        "class": "CPLD",
                        "arguments": {
                        "spi_device": "spi_urukul0",
                        "sync_device": None,
                        "io_update_device": "ttl_urukul0_io_update",
                        "refclk": 10000000.0,
                        "clk_sel": 1
                        }
                        }

                        device_db["urukul0_ch0"] = {
                        "type": "local",
                        "module": "artiq.coredevice.ad9910",
                        "class": "AD9910",
                        "arguments": {
                        "pll_n":42,
                        "pll_en":0,
                        "pll_vco":1,
                        "pll_cp":7,
                        "chip_select": 4,
                        "cpld_device": "urukul0_cpld",
                        "sw_device": "ttl_urukul0_sw0"