Your own statement that you don't sufficiently understand what phase accumulator is let me believe that pointers to existing information would help you sort out the basic concepts first before embarking on more advanced things. But as you say, you have already read and digested all the available information and I don't intend to repeat here that's already available elsewhere.
You may want to review your two questions. The only answers I can give you are unfortunately of very limited usefulness due to lack of any context, sufficiently complete code, description of what you want to achieve, accurate and understandable observation, and accurate description of expectations.
Is there no phase difference because the phase accumulator is set to crl=0?
I can't tell you why there is no phase difference because I don't know what you mean by the phrase. Please define what "phase difference" means for you. The two oscillators differ by 1 MHz and therefore (when running) their phase difference should increase by one turn per µs.
If we set clr=1 would there be a 10 ns phase between the two frequencies in the output?
"10 ns" is not a meaningful quantity for "phase difference" for any definition of the phrase that I am aware of.
As long as
clr=1 the phase accumulators will stay at 0. Only when deasserting
clr the accumulators start accumulating.
Maybe this is the answer that helps you understand things: "because one of the oscillator frequencies is 0".