We have started receiving an "invalid board id" error whenever phaser.init() is called in an experiment:

ERROR:worker(727,phaser_testing.py):root:Terminating with exception (ValueError: invalid board id)
Core Device Traceback:
Traceback (most recent call first):
  File "<artiq>/coredevice/phaser.py", line 273, column 13, in ... artiq.coredevice.phaser.Phaser.init<artiq.coredevice.phaser.Phaser>(...)
    raise ValueError("invalid board id")
    ^
  File "/home/artiq/artiq-master/repository/Marlo/phaser_testing.py", line 55, in artiq_worker_phaser_testing.SmoothPulse.fire(..., ...) (RA=+0x450)
    self.phaser0.init()
  File "<artiq>/coredevice/phaser.py", line 0, in ... artiq.coredevice.phaser.Phaser.init<artiq.coredevice.phaser.Phaser>(...) (RA=+0x1d10)
    <unknown>
ValueError(0): invalid board id

End of Core Device Traceback
Traceback (most recent call last):
  File "/nix/store/s92h8wmqf1qlkrjmsccsbd6jdynpfb2w-python3-3.12.10-env/lib/python3.12/site-packages/artiq/master/worker_impl.py", line 358, in main
    exp_inst.run()
  File "/home/artiq/artiq-master/repository/Marlo/phaser_testing.py", line 31, in run
    self.fire()
  File "/nix/store/s92h8wmqf1qlkrjmsccsbd6jdynpfb2w-python3-3.12.10-env/lib/python3.12/site-packages/artiq/language/core.py", line 54, in run_on_core
    return getattr(self, arg).run(run_on_core, ((self,) + k_args), k_kwargs)
           ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/nix/store/s92h8wmqf1qlkrjmsccsbd6jdynpfb2w-python3-3.12.10-env/lib/python3.12/site-packages/artiq/coredevice/core.py", line 172, in run
    self._run_compiled(kernel_library, embedding_map, symbolizer, demangler)
  File "/nix/store/s92h8wmqf1qlkrjmsccsbd6jdynpfb2w-python3-3.12.10-env/lib/python3.12/site-packages/artiq/coredevice/core.py", line 161, in _run_compiled
    self.comm.serve(embedding_map, symbolizer, demangler)
  File "/nix/store/s92h8wmqf1qlkrjmsccsbd6jdynpfb2w-python3-3.12.10-env/lib/python3.12/site-packages/artiq/coredevice/comm_kernel.py", line 734, in serve
    self._serve_exception(embedding_map, symbolizer, demangler)
  File "/nix/store/s92h8wmqf1qlkrjmsccsbd6jdynpfb2w-python3-3.12.10-env/lib/python3.12/site-packages/artiq/coredevice/comm_kernel.py", line 716, in _serve_exception
    raise python_exn
ValueError: invalid board id

I tried printing out the value of the board ID as read from the phaser, via board_id = self.phaser0.read8(PHASER_ADDR_BOARD_ID), and it prints out 255. Printout out the value stored in PHASER_ADDR_HW_REV prints 511, which is also incorrect.

Following another post on this topic, we checked the clock and data cables going to the phaser, and they are all properly connected. In the other post, the issue was with the clock frequency, but we have not overridden this anywhere and everything should just be using the Kasli-SOC's internal clock.

This occurred following the crate being power cycled. The phaser was working fine before power cycling the crate, and this error has appeared after, including through additional power cycles. We also tried with both the ARTIQ 8 gateware we recently switched to, and the ARTIQ7 gateware that originally came installed (we still had the original microSD cards), and it throws the same errors in both cases.

Hardware description:

{                                                                                                                                                
"target": "kasli_soc",                                                                                                                       
"min_artiq_version": "7.0",                                                                                                                  
"variant": "mitll7_marlo_master",                                                                                                            
"hw_rev": "v1.1",                                                                                                                            
"base": "master",                                                                                                                            
"core_addr": "169.254.13.38",                                                                                                                
"peripherals": [                                                                                                                                 
{                                                                                                                                                
"type": "suservo",                                                                                                                           
"sampler_ports": [1, 2],                                                                                                                     
"urukul0_ports": [3, 4],                                                                                                                     
"urukul1_ports": [5, 6],                                                                                                                     
"clk_sel": 2                                                                                                                             
},                                                                                                                                           
{                                                                                                                                                
"type": "urukul",                                                                                                                            
"dds": "ad9910",                                                                                                                             
"ports": [7, 8],                                                                                                                             
"clk_sel": 2,                                                                                                                                
"synchronization": true                                                                                                                  
},                                                                                                                                           
{                                                                                                                                                
"type": "phaser",                                                                                                                            
"ports": [9]                                                                                                                             
},                                                                                                                                           
{                                                                                                                                                
"type": "dio",                                                                                                                               
"ports": [10],                                                                                                                               
"board": "DIO_SMA",                                                                                                                          
"bank_direction_low": "input",                                                                                                               
"bank_direction_high": "output"                                                                                                          
}                                                                                                                                        
]                                                                                                                                        
}

Relevant portions of device_db.py:

device_db = {
    "core": {
        "type": "local",
        "module": "artiq.coredevice.core",
        "class": "Core",
        "arguments": {"host": core_addr, "ref_period": 1e-09, "target": "cortexa9"},
    },
    "core_log": {
        "type": "controller",
        "host": "0.0.0.0",
        "port": 1068,
        "command": "aqctl_corelog -p {port} --bind {bind} " + core_addr,
    },
    "core_moninj": {
        "type": "controller",
        "host": "0.0.0.0",
        "port_proxy": 1383,
        "port": 1384,
        "command": "aqctl_moninj_proxy --port-proxy {port_proxy} --port-control {port} --bind {bind} "
        + core_addr,
    },
    "core_cache": {
        "type": "local",
        "module": "artiq.coredevice.cache",
        "class": "CoreCache",
    },
    "core_dma": {"type": "local", "module": "artiq.coredevice.dma", "class": "CoreDMA"},
    "i2c_switch0": {
        "type": "local",
        "module": "artiq.coredevice.i2c",
        "class": "I2CSwitch",
        "arguments": {"address": 0xE0},
    },
    "i2c_switch1": {
        "type": "local",
        "module": "artiq.coredevice.i2c",
        "class": "I2CSwitch",
        "arguments": {"address": 0xE2},
    },
}

...

device_db["phaser0"] = {
    "type": "local",
    "module": "artiq.coredevice.phaser",
    "class": "Phaser",
    "arguments": {
        "channel_base": 0x000013,
        "miso_delay": 1,
    },
}