Hi,
We are trying to write an experimental sequence that uses artiq ttl input to time tag the incoming pulses in each experiment cycle (like what a time tagger does). Meanwhile, in each cycle, we are also using ttl output to send out some trigger pulses.
Here's our simplified code:
with parallel:
for bin_ in range(n_bins):
self.core.break_realtime()
t_count = self.ttl2.gate_rising(t_bins*ns)
count = self.ttl2.count(t_count)
self.time_tag(bin_,count)
with sequential:
self.core.break_realtime()
#### experiment trigger pulses
self.ttl8.on()
delay(t_load*us)
......
self.update_timetag_hist()
However, we have found that if we set the bin width (t_bins) to be less than 1us, the actual run time is much longer than the expected experiment sequence duration for a single loop. (For a 100ns bin width, each run takes 14s for a 3s sequence for a 100ns bin width). This also makes us worry about the time synchronization between the two parallel blocks.
I was wondering whether there was any advice as to the best way to achieve this time tag task with artiq ?
Thank you for your help in advance.