Testbench not working

frankbuss

I have this code:

#!/usr/bin/env python3

from migen import *

class Test(Module):
    def __init__(self, clk):
        self.clock_domains.cd_clk = ClockDomain()
        self.comb += self.cd_clk.clk.eq(clk)

        self.fx = fx = Signal(3)
        self.sync.clk += [
            fx.eq(fx + 1),
            If (fx == 7, fx.eq(0)),
        ]

def testbench(dut):
    for i in range(10):
        yield clk.eq(i & 1)
        yield
        print("clk:{} fx:{}".format((yield clk), (yield dut.fx)))

clk = Signal()
dut = Test(clk)
run_simulation(dut, testbench(dut))

but when I run it, it shows this:

clk:0 fx:0
clk:1 fx:0
clk:0 fx:0
clk:1 fx:0
clk:0 fx:0
clk:1 fx:0
clk:0 fx:0
clk:1 fx:0
clk:0 fx:0
clk:1 fx:0

Why is fx not incremented? And how would I simulate the system clock, if want to do this?

sb10q

You need to give run_simulation a list of clocks and their frequencies. The simulator does not look for externally-generated rising edges in the clock signals, it drives the clocks itself.