Phaser has delayed output

ajras

Hi all!

I've got a question about the best practices for correcting a delayed output from the phaser. Right now we're seeing a ₁.8us delay between scheduling the phaser to output a frequency and the actual signal coming out of the port. The comparison is made by outputting a ttl pulse at the same time we set the amplitude of one of the oscillators. In the docs it says the phaser's output is deterministic wrt to the RTIO timeline, so my question is what's the best practice for matching the delay?

Thanks!
AJ

rjo

Delay the ttl events or advance the phaser events.
There is also a latency compensation in the RTIO channels that could be used.
YMMV

ajras

Thanks! Adding delays seems to be workable

How does this kind of delay relate to phase accumulation? Let’s say we clear the phase accumulation then turn on the phaser wait ₁.8us then see it output. Where should we expect the zero phase point in the output signal wrt to the RTIO timeline. Is it before (so 1.8us before it shows up on the scope) or after the 1.8us delay (right when the signal appears on the scope)?