Hi all!
I've got a question about the best practices for correcting a delayed output from the phaser. Right now we're seeing a 1.8us delay between scheduling the phaser to output a frequency and the actual signal coming out of the port. The comparison is made by outputting a ttl pulse at the same time we set the amplitude of one of the oscillators. In the docs it says the phaser's output is deterministic wrt to the RTIO timeline, so my question is what's the best practice for matching the delay?
Thanks!
AJ