Specifying clock domain for sub-module in a multi-clock parent module.

annguyen1991

Hi,
May I ask you how to specify which clock domain is used by a sub-module?

For example, if in my parent module, I have two clock domains.
I then create a sub-module, how can specify the sub-module to working on a certain clock domain.

sb10q

Use ClockDomainsRenamer.

annguyen1991

Thanks for your reply.

I search litex github for an example of using ClockDomainsRenamer. Here is a piece of code that I got

read_fifo = ClockDomainsRenamer({"write": "usb", "read": "sys"}) \ (stream.AsyncFIFO(phy_description(dw), fifo_depth)) read_buffer = ClockDomainsRenamer("usb")(stream.SyncFIFO(phy_description(dw), 4))

As I understand, in the first line, AsyncFIFO object has two clock domains read and write. Its write clock domain will be usb clock domain of parent module and its read clock domain will be sys clock domain of parent module.
In the second line, SyncFIFO has only one clock domain and it will be assigned to usb clock domain of parent module.

Am I got it right?

sb10q

Yes, that's correct.