fevi_at_jila Hi, What is the significance of the dummy_s and dummy_d registers in generated verilog code? Are those just delimiters for modules and their interfaces or is there something more one can do with them? Thanks for the help! Felix
sb10q They are only here to get the @always blocks to run once at startup when the Verilog file is simulated, and initialize the other registers. They don't do anything in synthesis.