This is somewhat off-topic, but do you know why the ext0_bypass clock is so noisy tompared to the 1:1 PLL? We previously saw the same here (with a high-quality Wenzel 125 MHz reference), but I never had time to dig into what is going on there. Is this just a pecularity of the Si5324? IIRC, I saw significantly worse broadband noise at 25 MHz offset frequencies.
In fact, in various setups here we even saw crashes and DRTIO corruption when using ext0_bypass, to the point where the manual should probably warn against this (at least if substantiated).
