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  • WRPLL phase noise comparison on standalone Kasli SOC

WRPLL clock recovery was added in ARTIQ 8, and here's the phase noise comparison between Si5324 and WRPLL on a standalone Kasli SOC:




For detail on using WRPLL clock recovery please see the Clocking section on M-labs manual.

morgan changed the title to WRPLL phase noise comparison on standalone Kasli SOC .

Hi, are you using a WR-switch to provide synchronization to the Kasli?
Would it make a difference if using a Low-Jitter version of the WR-switch? (compared to the standard WR-switch)

    This is somewhat off-topic, but do you know why the ext0_bypass clock is so noisy tompared to the 1:1 PLL? We previously saw the same here (with a high-quality Wenzel 125 MHz reference), but I never had time to dig into what is going on there. Is this just a pecularity of the Si5324? IIRC, I saw significantly worse broadband noise at 25 MHz offset frequencies.

    In fact, in various setups here we even saw crashes and DRTIO corruption when using ext0_bypass, to the point where the manual should probably warn against this (at least if substantiated).

      awallin No, the WRPLL is running on the Kasli SoC. It is a clock recovery method using DDMTD and the Si549 oscillators instead of using the Si5324.

      dpn I am not sure why either. From Si5324 datasheet, it didn't mention any performance impact (e.g. phase noise, jitter etc) when using bypass mode.

      4 days later

      dpn In fact, in various setups here we even saw crashes and DRTIO corruption when using ext0_bypass, to the point where the manual should probably warn against this (at least if substantiated).

      Let's keep random bug reports out of the manual. Better just fix them.

      • dpn replied to this.
        2 months later

        dpn Thank you for your comment! May I please ask you and the community in general a few questions?

        1. Do you have any experience with supplying a 10 MHz reference to the Kasli / Kasli SoC? How much worse is the clock signal phase noise compared to using your 125 MHz reference?
        2. How does the user profit from lower phase noise on the clock signal of the Kasli / Kasli SoC? I assume the Urukul phase noise becomes lower, but are there also other advantages?
        3. Would you say buying a high-quality 125 MHz reference is worth it?
        • dpn replied to this.
          16 days later

          dtsevas

          People here are using both variants. Whether it's worth it really depends on how much you care about the phase noise floor at higher offset frequencies vs. close-in. Some very high-fidelity single-qubit gates here have been done with a 10 MHz reference (but using Kasli only to generate IQ signals on top of an external high-quality LO for the bulk of the qubit splitting). There are probably phase noise plots in some of the design discussions, but I haven't made the comparison myself recently. Overall, if you don't have a way of measuring the effect on the RF outputs yourself (a good phase noise analyser/…), it's probably not worth it to "preemptively" spend significant amounts of money on high-quality oscillators for phase noise alone.

          Another reason to use a 125 MHz reference might be in order to get phase determinism between multiple Kaslis/… that are not part of the same system by avoiding the fractional-N PLL.

          sb10q Let's keep random bug reports out of the manual. Better just fix them.

          Of course – ideally. It would be great if somebody had the bandwidth to figure out what is going on here. I don't, for one.

          For now, the manual appears to steer people into a direction that we have multiple reports doesn't work well. We can avoid sending people down a wrong path even without turning the manual into a collection of bug reports.