On Artiq 7 and a standalone Kasli SoC v.1.1, artiq_coremgmt reboot produces this python error log:

m1@m1-notebook-1:~/workspace/artiq_system_description_files_TESTING/kasli_soc_standalone_8_sed_lanes_no_peripherals$ artiq_coremgmt reboot
Traceback (most recent call last):
  File "/nix/store/hnfph2qjhw430yyb47d44x8dwy30h1n6-python3.9-artiq-7.8208.38c72fd/bin/.artiq_coremgmt-wrapped", line 9, in <module>
    sys.exit(main())
  File "/nix/store/hnfph2qjhw430yyb47d44x8dwy30h1n6-python3.9-artiq-7.8208.38c72fd/lib/python3.9/site-packages/artiq/frontend/artiq_coremgmt.py", line 142, in main
    mgmt.reboot()
  File "/nix/store/hnfph2qjhw430yyb47d44x8dwy30h1n6-python3.9-artiq-7.8208.38c72fd/lib/python3.9/site-packages/artiq/coredevice/comm_mgmt.py", line 193, in reboot
    self._read_expect(Reply.RebootImminent)
  File "/nix/store/hnfph2qjhw430yyb47d44x8dwy30h1n6-python3.9-artiq-7.8208.38c72fd/lib/python3.9/site-packages/artiq/coredevice/comm_mgmt.py", line 113, in _read_expect
    header = self._read_header()
  File "/nix/store/hnfph2qjhw430yyb47d44x8dwy30h1n6-python3.9-artiq-7.8208.38c72fd/lib/python3.9/site-packages/artiq/coredevice/comm_mgmt.py", line 107, in _read_header
    ty = Reply(*struct.unpack("B", self._read(1)))
  File "/nix/store/hnfph2qjhw430yyb47d44x8dwy30h1n6-python3.9-artiq-7.8208.38c72fd/lib/python3.9/site-packages/artiq/coredevice/comm_mgmt.py", line 100, in _read
    rn = self.socket.recv(min(8192, length - len(r)))
ConnectionResetError: [Errno 104] Connection reset by peer

artiq_coremgmt reboot also produces the last 3 lines in this artiq_coremgmt log:

[     0.000067s]  INFO(runtime): NAR3/Zynq7000 starting...
[     0.005173s]  INFO(runtime): gateware ident: kasli_soc_standalone_8_sed_lanes_no_peripherals
[     0.018852s]  INFO(libboard_zynq::i2c): PCA9548 detected
[     0.043725s]  INFO(runtime::rtio_clocking): using internal 125MHz RTIO clock
[     0.434645s]  INFO(libboard_artiq::si5324): waiting for Si5324 lock...
[     5.842791s]  INFO(libboard_artiq::si5324):   ...locked
[     5.849989s]  INFO(runtime::rtio_clocking): RTIO PLL locked
[     5.860744s]  INFO(libboard_zynq::i2c): PCA9548 detected
[     5.894306s]  INFO(runtime::comms): network addresses: MAC=fc-0f-e7-0f-52-45 IPv4=192.168.1.30 IPv6-LL=fe80::fe0f:e7ff:fe0f:5245 IPv6: no configured address
[    10.421082s]  INFO(libboard_zynq::eth): eth: got Link { speed: S1000, duplex: Full }
[    31.428761s]  INFO(runtime::mgmt): received connection
[    43.269702s]  INFO(runtime::mgmt): received connection
[    43.276564s]  WARN(runtime::mgmt): connection terminated: UnrecognizedPacket
[    62.257873s]  INFO(runtime::mgmt): received connection

Other commands, such as artiq_coremgmt config write -s rtio_clock int_125 and artiq_coremgmt config read rtio_clock, have the desired effect and produce clean logs.

I ran into this problem while trying to flash my Kasli SoC via ethernet. Please help, we really need to be able to flash our Kasli SoCs via Ethernet and we don't know how to debug this!

Background info:

  • Ubuntu Desktop 22.04.5 LTS
  • Xilinx unified installer 2022.2 with extra content: Vivado, Vitis, Artix-7, Zynq-7000
  • artiq/release-7
  • artiq-zynq/release-7
  • system description file kasli_soc_standalone_8_sed_lanes_no_peripherals.json:
{
    "target"            : "kasli_soc",
    "hw_rev"            : "v1.1",
    "base"              : "standalone",
    "sed_lanes"         : 8,
    "rtio_frequency"    : 125e6,
    "core_addr"         : "10.0.0.50",
    "min_artiq_version" : "7.0",
    "variant"           : "kasli_soc_standalone_8_sed_lanes_no_peripherals",
    "peripherals"       : []
}
  • Vivado log was full of warnings but no errors. Please download it from https://datashare.mpcdf.mpg.de/s/P9oVn5Dq71LDIDa because the forum is not letting me upload it.
  • device_db.py constructed via artiq_ddb_template kasli_soc_standalone_8_sed_lanes_no_peripherals.json > device_db.py. Output:

# Autogenerated for the kasli_soc_standalone_8_sed_lanes_no_peripherals variant
# core_addr = "10.0.0.50"
core_addr = "192.168.1.30"

device_db = {
    "core": {
        "type": "local",
        "module": "artiq.coredevice.core",
        "class": "Core",
        "arguments": {"host": core_addr, "ref_period": 1e-09, "target": "cortexa9"},
    },
    "core_log": {
        "type": "controller",
        "host": "::1",
        "port": 1068,
        "command": "aqctl_corelog -p {port} --bind {bind} " + core_addr
    },
    "core_moninj": {
        "type": "controller",
        "host": "::1",
        "port_proxy": 1383,
        "port": 1384,
        "command": "aqctl_moninj_proxy --port-proxy {port_proxy} --port-control {port} --bind {bind} " + core_addr
    },
    "core_cache": {
        "type": "local",
        "module": "artiq.coredevice.cache",
        "class": "CoreCache"
    },
    "core_dma": {
        "type": "local",
        "module": "artiq.coredevice.dma",
        "class": "CoreDMA"
    },

    "i2c_switch0": {
        "type": "local",
        "module": "artiq.coredevice.i2c",
        "class": "I2CSwitch",
        "arguments": {"address": 0xe0}
    },
    "i2c_switch1": {
        "type": "local",
        "module": "artiq.coredevice.i2c",
        "class": "I2CSwitch",
        "arguments": {"address": 0xe2}
    },
}

# standalone peripherals

device_db["led0"] = {
    "type": "local",
    "module": "artiq.coredevice.ttl",
    "class": "TTLOut",
    "arguments": {"channel": 0x000000}
}

device_db["led1"] = {
    "type": "local",
    "module": "artiq.coredevice.ttl",
    "class": "TTLOut",
    "arguments": {"channel": 0x000001}
}
dtsevas changed the title to `artiq_coremgmt reboot` fails! .

Quoting Creotech's answer to our email:

Same issue 2 years ago: artiq_coremgmt reboot broken #178
Fix via pull request 2 years ago: Implement reboot for artiq_coremgmt #202
Commit with fix 2 years ago: 1220268822e333e0ec78ef151f5e53e514c60b72 (Implement reboot for artiq_coremgmt)

"I see that you're using artiq-7. The aforementioned commit was not merged back into release-7 of artiq-zynq so you'll have to include it in one of two ways: either upgrade your systems to artiq release-8 (both artiq and artiq-zynq) or cherry-pick that commit to include that functionality in your builds."


Our lab is very likely upgrading to Artiq 8 in the next few days.

So it is.
Let us know how is the upgrade doing.