With a freshly cloned artiq repo (version 8 branch), the firmeware build
python -m artiq.gateware.targets.kasli test.json
fails with
Command: write_bitstream -force top.bit
...
ERROR: [DRC PDCN-2721] IBUFDS_GT_loads_clock_region: IBUFDS_GTE2 IBUFDS_GTE2 drives MMCME2_ADV MMCME2_BASE in a different clock region and must do so using local routing resources which may negatively affect clock performance. Use CLOCK_DEDICATED_ROUTE set to FALSE to indicate this is intended.
ERROR: [DRC PDCN-2721] IBUFDS_GT_loads_clock_region: IBUFDS_GTE2 IBUFDS_GTE2 drives PLLE2_ADV PLLE2_BASE in a different clock region and must do so using local routing resources which may negatively affect clock performance. Use CLOCK_DEDICATED_ROUTE set to FALSE to indicate this is intended.
when generating the top bit. This happens for all master/satman/kasli HW version configurations I came up with including this minimal test build (test.json):
{
"target": "kasli",
"variant": "test",
"hw_rev": "v2.0",
"base": "satellite",
"peripherals": [
{
"type": "dio",
"board": "DIO_BNC",
"ports": [
0
],
"hw_rev": "v1.2",
"bank_direction_low": "input",
"bank_direction_high": "output"
}
]
}
I did not find an issue in the git. So is it only me having this issue? Could it be Vivado configuration or something? Any help would be appreciated.