Hello everyone, i'm trying to figure out the communication on EEM0 of Fastino. Github states that it uses some kind of 8-pin SPI with CLK on EEM0_0, MOSI on EEM0_1 to EEM0_6 and MISO on EEM0_7.

I'm wondering if the master is always fixed kasli and fastino always fixed slave, i.e. if the clock is generated by Kasli or Fastino and if MISO and MOSI always have the same transmission directions for LVDS (MISO => Fastino to Kasli, MOSI => Kasli to Fastino).

It appears that EEM1 isn't used at all by default on fastino, is that correct? Or is there instances where two EEM connectors are needed?

Would gladly appreciate any help, thanks!

It's more like camera link. EEM1 is not used. MISO is not implemented in the Kasli side.

    rjo cool thanks. So the transmission direction doesnt change? LVDS0 to LVDS6 are always going from Kasli to Fastino?

    Also: what is the maximum propagation delay between kasli and fastino that can be tolerated? is 4 ns delay still tolerated?

      Direction is fixed. Delay is irrelevant as long as it is not jittery and matched between lanes.

        rjo do you know what's the maximum permitted inter pair skew between the lvds pairs?

          Never measured it. It'll be 4 ns/2 minus S/H of the ice40 input serdes, existing board/wire skew, Kasli CLK and output serdes jitter, ice40 buffer and PLL jitter, Kasli FPGA output DATA serdes jitter. Back in the day I tried a long (10m?) spooled ribbon cable to degrade SI and that worked fine.
          There is some preliminary code to do online automatic inter-lane alignment but I don't think that was ever tested or needed.