I currently try to understand the examples in AD9910 and its cpld codes and make sure we can develop our code. Yet I still have some confusion about methods.
such as the codes below:
@kernal
def configure_ram_mode(self, dds):
self.core.break_realtime()
dds.set_cfr1(ram_enable=0)
self.cpld.io_update.pulse_mu(8)
self.cpld.set_profile(0)
# Enable the corresponding RAM profile
# Profile 0 is the default
dds.set_profile_ram(start=0, end=len(self.asf_ram)-1,
step=250, profile=0, mode=RAM_MODE_CONT_RAMPUP)
self.cpld.io_update.pulse_mu(8)
dds.amplitude_to_ram(self.amp, self.asf_ram)
dds.write_ram(self.asf_ram)
self.core.break_realtime()
dds.set(frequency=5*MHz, ram_destination=RAM_DEST_ASF)
# Pass osk_enable=1 to set_cfr1() if it is not an amplitude RAM
dds.set_cfr1(ram_enable=1, ram_destination=RAM_DEST_ASF)
self.cpld.io_update.pulse_mu(8)
I didn't see the related explaination about classcpld.io_updatein artiq manual. And I don't sure whether what is the purpose to call cpld.io_update.pulse_mu and the difference between the RAM mode like 'RAM_MODE_CONT_RAMPUP' and the other modes.
Could someone provide some resource or explaination which would help me to understand these things?
Thank you for your precious help in advance.