Hi together,
I am trying to get a frequency sweep out of my Urukul AD9910. I am using RAM-Mode and everything seems to work kind of nicely. Here is a snippet of my code, it is a bit messy, but mainly follows what was posted here.
@kernel
def do(self):
# Initialize
self.core.reset()
self.dds.init()
self.dds.cpld.init()
self.core.break_realtime()
self.dds.cpld.io_update.pulse(100*ns)
self.dds.set(amplitude = 1., frequency = self.base_freq)
self.core.break_realtime()
# Prepare RAM profile
self.dds.set_cfr1() #disable RAM for writing data
self.dds.cpld.io_update.pulse_mu(8) #I/O pulse to enact RAM change
self.dds.set_profile_ram(start=0, end=self.N-1, step=self.T_step, profile=0, mode=ad9910.RAM_MODE_RAMPUP)
self.dds.cpld.set_profile(0)
self.dds.cpld.io_update.pulse_mu(8)
# Write Data to RAM
delay(50*us)
self.dds.write_ram(self.f_ram) #This is a profile previously created
delay(100*us)
# Enable RAM mode
self.dds.set_cfr1(internal_profile=0,ram_destination=ad9910.RAM_DEST_FTW, ram_enable=1,
manual_osk_external=0, osk_enable=1, select_auto_osk=0)
self.dds.set(amplitude = 1., frequency = self.base_freq)
self.dds.cfg_sw(True)
self.dds.set_att(self.attenuation*dB)
self.core.break_realtime()
self.dds.cpld.io_update.pulse_mu(8) # This should start the pulse
self.ttl.pulse(100*ns) # TTL-pulse for triggering the scope, should start at the same time???
delay(50*ms)
self.dds.cfg_sw(False)
It also seems to work fine, but I see that the TTL-Pulse comes around 100ns earlier than my modulation pulse that should start with the io_update pulse. Why is that and how do I get rid of that delay? Or, if this delay cannot be gotten rid of, how do I know the exact time of that delay?
