Hi together,

I am trying to get a frequency sweep out of my Urukul AD9910. I am using RAM-Mode and everything seems to work kind of nicely. Here is a snippet of my code, it is a bit messy, but mainly follows what was posted here.

    @kernel
    def do(self):
        # Initialize
        self.core.reset()
        self.dds.init()
        self.dds.cpld.init()
        self.core.break_realtime()

        self.dds.cpld.io_update.pulse(100*ns)
        self.dds.set(amplitude = 1., frequency = self.base_freq)
        self.core.break_realtime()

        # Prepare RAM profile
        self.dds.set_cfr1() #disable RAM for writing data
        self.dds.cpld.io_update.pulse_mu(8) #I/O pulse to enact RAM change
        self.dds.set_profile_ram(start=0, end=self.N-1, step=self.T_step, profile=0, mode=ad9910.RAM_MODE_RAMPUP)
        self.dds.cpld.set_profile(0)
        self.dds.cpld.io_update.pulse_mu(8)
        
        # Write Data to RAM
        delay(50*us)
        self.dds.write_ram(self.f_ram) #This is a profile previously created
        delay(100*us)

        # Enable RAM mode
        self.dds.set_cfr1(internal_profile=0,ram_destination=ad9910.RAM_DEST_FTW, ram_enable=1,
                          manual_osk_external=0, osk_enable=1, select_auto_osk=0)
        self.dds.set(amplitude = 1., frequency = self.base_freq)
        self.dds.cfg_sw(True)
        self.dds.set_att(self.attenuation*dB)
        self.core.break_realtime()
        
        self.dds.cpld.io_update.pulse_mu(8) # This should start the pulse
        self.ttl.pulse(100*ns)     # TTL-pulse for triggering the scope, should start at the same time???

        delay(50*ms)
        self.dds.cfg_sw(False)

It also seems to work fine, but I see that the TTL-Pulse comes around 100ns earlier than my modulation pulse that should start with the io_update pulse. Why is that and how do I get rid of that delay? Or, if this delay cannot be gotten rid of, how do I know the exact time of that delay?

    simonschey I am trying to get a frequency sweep out of my Urukul AD9910. I am using RAM-Mode

    Maybe try ARTIQ-9 with the patches in PRs that let you use the DRG instead. We really could use more beta-testers.

        simonschey I see that the TTL-Pulse comes around 100ns earlier than my modulation pulse that should start with the io_update pulse. Why is that and how do I get rid of that delay? Or, if this delay cannot be gotten rid of, how do I know the exact time of that delay?

        A significant part of the latency is probably specified by the "data latency" specifications of AD9910.

        1 SYSCLK cycle should mean 1 ns if you are using default settings.

            sb10q I have looked into the DRG, but as far as I know, the DRG only lets me do a linear ramp between two frequencies, right? I need something more complicated, my frequency should sweep proportional to sin(t)2

              occheung I have looked at this page before, thanks. It seems like the line that is relevant to me would be the first one in "Data Latency using RAM Mode" which is 94ns. But am I missing any additional delay? I am observing something like 100-102ns if I measure correctly...

                6 days later

                From Figure 49 of the datasheet, I think there is a further 4 ns to 8 ns (1 to 2 cycles of SYNC_CLK) worth of delay needed to transfer configurations from the I/O buffer to the registers.