I tried to use the new Urukul features, but now a simple experiment that switches on a single DDS channel for 5 microseconds outputs a much much smaller voltage amplitude than before. The scope now shows 80 mV peak-to-peak with attenuation set to 0.0
and amplitude set to 1.0
, compared to almost 1 Volt peak-to-peak before.
Could that be caused by a system description file without "proto_rev"
keyword, where the default is 8
? I will try to re-compile with "proto_rev" : 9
and see if that fixes the DDS output amplitude.
"The new system" below lists all changes I made for the upgrade. Did I miss any changes that are required for the new Urukul features?
The new system
- Urukuls v1.5.4 are flashed with urukul-pld commit 50d24c0e69791efc2a0f588980d151c3964a5283 from 2025 Apr 9.
- Kasli SoC v1.1.1 is flashed with artiq-zynq commit 7df7335cce41bb2d52832c25f8af5be80f9744ab from 2025 May 21. In my new system description file, I did not use the
"proto_rev"
keyword, that was introduced in artiq commit (c34c2c29ab060abec0b6f8ea336f46dd11ddd68a)[https://github.com/m-labs/artiq/commit/c34c2c29ab060abec0b6f8ea336f46dd11ddd68a] from 2025 Apr 22. - Host is using artiq commit d7a380db01b05ef7b5d372584ab2f3568ea3b777 from 2025 May 16.
The experiment
from artiq.language.environment import EnvExperiment
from artiq.language.core import kernel, delay, now_mu
from artiq.language.units import ns, us, ms, s, MHz, V
from artiq.coredevice.i2c import i2c_write_byte
from artiq.coredevice.kasli_i2c import port_mapping
from artiq.coredevice.ad9910 import PHASE_MODE_CONTINUOUS
# Maps Kasli EEM port indices that are visible on the PCB
# to actual electrical port(?) indices that need to be passed to the FPGA.
KASLI_I2C_BOARD_TO_PORT_MAPPING = [port%8 for port in port_mapping.values()]
# for `artiq.coredevice.i2c.i2c_write_byte(busno, busaddr, data, ack=True)`
# and `artiq.coredevice.i2c.i2c_read_byte(busno, busaddr)`
DIO_SMA_BUS_NUMBER = 0
DIO_SMA_BUS_ADDRESS = 0x7c # = 124 (decimal) or 01111100 (binary)
class DRGAmplitudeTest(EnvExperiment):
def build(self):
self.setattr_device("core") # artiq.coredevice.core.Core
device_db = self.get_device_db() # dict, DO NOT EDIT!
self.n_kasli_socs = 1 + len(device_db["core"]["arguments"]["satellite_cpu_targets"])
self.setattr_device("i2c_switch0") # artiq.coredevice.i2c.I2CSwitch
self.setattr_device("ttl0") # artiq.coredevice.ttl.TTLInOut
self.setattr_device("urukul0_cpld") # artiq.coredevice.urukul.CPLD
self.setattr_device("urukul0_ch0") # artiq.coredevice.ad9910.AD9910
@kernel
def init(self):
for i in range(self.n_kasli_socs):
while not self.core.get_rtio_destination_status(i):
pass
self.core.reset()
self.core.break_realtime()
self.i2c_switch0.set(channel = KASLI_I2C_BOARD_TO_PORT_MAPPING[0])
delay(1*us)
i2c_write_byte(
busno = DIO_SMA_BUS_NUMBER,
busaddr = DIO_SMA_BUS_ADDRESS,
data = 0
)
delay(1*us)
self.i2c_switch0.unset()
self.core.break_realtime()
self.ttl0.output()
delay(1*us)
self.ttl0.off()
delay(1*us)
self.urukul0_cpld.init()
delay(1*us)
self.urukul0_ch0.sw.off()
delay(1*us)
self.urukul0_ch0.init()
delay(1*us)
self.urukul0_ch0.set_phase_mode(PHASE_MODE_CONTINUOUS)
delay(1*us)
self.urukul0_ch0.set_att(0.0)
delay(1*us)
self.core.wait_until_mu(now_mu())
@kernel
def run(self):
self.init()
self.core.reset()
self.core.break_realtime()
self.urukul0_ch0.set(180*MHz, 0.0, 1.0)
self.urukul0_ch0.sw.on()
self.ttl0.on()
delay(5*us)
self.urukul0_ch0.sw.off()
self.ttl0.off()
delay(5*us)