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Sinara

Urukul/AD9910: coherent phase updates in RAM mode
Mirny + artiq_sinara_tester: "MUXOUT not low"
Running ARTIQ from Python console
Phaser/Urukul phase tracking
Fastino precision programmable CIC interpolator
artiq_sinara_tester not working
Mirny v1.0 (ADF5356) outputs not longer working after months of operation
Large mismatch between PC clock time and Kasli kernel time
Urukul Ramping Step
Missing artiq-board-kasli-ubirmingham package
Fast saving results problem
Up to date development instructions?
artiq_flash error, artiq_81ll_wqc_top.bit contents differ
Compiler Error with custom Zotino Channel wrapper
Urukul/AD9910: phase accumulator reset upon profile change?
What type of error does the error light on Kasli 2.0 indicate?
Urukul: parameter set speed / delay
Clocker Input Frequency
breakout for Sinara 2245 LVDS RJ45 TTL card
Reading status of a dds

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