Sinara

D
Automated firmware building for the Kasli SoC
- Giving a tutorialARTIQSinara
- dtsevas replied 7 Feb
2 replies
D
artiq-zynq compilation from December 2024 crashes?
- Asking for helpARTIQSinara
- sb10q replied 7 Feb
1 reply
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How do I obtain Vivado build logs for my Kasli SoC firmware?
- Giving a tutorialSinara
- dtsevas started 2 Feb
0 replies
F
Confusing with example codes
- Asking for helpARTIQSinara
- FENIX replied 25 Jan
2 replies
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Arbitrary keys in system description file?
- Asking for helpARTIQSinara
- architeuthis replied 17 Jan
1 reply
K
(PHASER) Simulatenous signals beyond the +-10MHz range of DUC frequency
- Asking for helpARTIQSinara
- rjo replied 17 Jan
2 replies
K
Trying to generate some basic sine waves with phaser
- Asking for helpARTIQSinara
- karps77 replied 17 Jan
2 replies
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Switch to Vivado 2024?
- Asking for helpSinara
- dtsevas replied 16 Jan
5 replies
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Upload device map to satellites?
- Asking for helpARTIQSinara
- occheung replied 16 Jan
3 replies
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Noise on Fastino output?
- Asking for helpARTIQSinara
- sb10q replied 16 Jan
1 reply
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Urukul v1.5.4: LD5, LD6, LD8 and LD2 remain dark, `AD9910.init()` crashes
- Asking for helpSinara
- dtsevas replied 15 Jan
2 replies
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Can 4412DDS / AD9912 set atte individually for every channel?
- Asking for helpARTIQSinara
- occheung replied 2 Jan
1 reply
L
Fastino <-> Kasli Communication
- Asking for helpARTIQSinara
- rjo replied Dec 17, 2024
5 replies
R
Allied Vision Camera control with ARTIQ
- Asking for helpARTIQSinara
- RyanEverly replied Dec 9, 2024
2 replies
G
artiq8 gateware mismatch
- Asking for helpSinara
- occheung replied Dec 9, 2024
7 replies
M
Stabilizer does not respond anymore after updating /net/broker
- Asking for helpSinara
- rjo replied Dec 2, 2024
5 replies
S
kc705 build gateware error
- Asking for helpARTIQSinara
- sb10q replied Nov 29, 2024
1 reply
A
Running one Urukul channel deattenuates the other channel during a new run
- Asking for helpARTIQSinara
- dpn replied Nov 27, 2024
4 replies
A
"FPGA DONE" LED location
- Asking for helpSinara
- architeuthis replied Nov 26, 2024
3 replies
Decoding via PuTTY
- Asking for helpARTIQSinara
- multi131 replied Nov 21, 2024
1 reply

Sinara

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Automated firmware building for the Kasli SoC

artiq-zynq compilation from December 2024 crashes?

How do I obtain Vivado build logs for my Kasli SoC firmware?

Confusing with example codes

Arbitrary keys in system description file?

(PHASER) Simulatenous signals beyond the +-10MHz range of DUC frequency

Trying to generate some basic sine waves with phaser

Switch to Vivado 2024?

Upload device map to satellites?

Noise on Fastino output?

Urukul v1.5.4: LD5, LD6, LD8 and LD2 remain dark, `AD9910.init()` crashes

Can 4412DDS / AD9912 set atte individually for every channel?

Fastino <-> Kasli Communication

Allied Vision Camera control with ARTIQ

artiq8 gateware mismatch

Stabilizer does not respond anymore after updating /net/broker

kc705 build gateware error

Running one Urukul channel deattenuates the other channel during a new run

"FPGA DONE" LED location

Decoding via PuTTY