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D
Transfer values to master once and then access them from all kernel functions
Asking for help
ARTIQ
Sinara
dtsevas
replied
28 Feb
4
4 replies
L
EEPROM aliasing when using DRTIO
General
ARTIQ
Sinara
KlausZipfel
replied
28 Feb
22
22 replies
D
Number of packets before reply from satellite
Asking for help
Sinara
dtsevas
started
24 Feb
0
0 replies
D
Which SFP speeds for different Kasli & Kasli SoC versions?
Asking for help
Sinara
dtsevas
replied
24 Feb
4
4 replies
D
Kasli SoC `aux packet error (link down)` and `DrtioError(LinkDown)`
Asking for help
ARTIQ
Sinara
dtsevas
replied
24 Feb
3
3 replies
J
Ramp Function with SUServo
Asking for help
Sinara
dpn
replied
23 Feb
1
1 reply
P
Control Stabilizer from Kasli
General
ARTIQ
Sinara
Philipp
started
20 Feb
0
0 replies
L
Looking for stabilizer mezzanine with AD9910 (or similar) DDS
Asking for help
Sinara
rjo
replied
18 Feb
7
7 replies
L
Inquiry about Bidirectional TTL in Output Mode
Asking for help
ARTIQ
Sinara
massirossi
replied
14 Feb
7
7 replies
D
DRTIO satellite: Kasli SoC vs. Kasli?
Asking for help
Sinara
dtsevas
replied
11 Feb
2
2 replies
D
Automated firmware building for the Kasli SoC
Giving a tutorial
ARTIQ
Sinara
dtsevas
replied
7 Feb
2
2 replies
D
artiq-zynq compilation from December 2024 crashes?
Asking for help
ARTIQ
Sinara
sb10q
replied
7 Feb
1
1 reply
D
How do I obtain Vivado build logs for my Kasli SoC firmware?
Giving a tutorial
Sinara
dtsevas
started
2 Feb
0
0 replies
F
Confusing with example codes
Asking for help
ARTIQ
Sinara
FENIX
replied
25 Jan
2
2 replies
D
Arbitrary keys in system description file?
Asking for help
ARTIQ
Sinara
architeuthis
replied
17 Jan
1
1 reply
K
(PHASER) Simulatenous signals beyond the +-10MHz range of DUC frequency
Asking for help
ARTIQ
Sinara
rjo
replied
17 Jan
2
2 replies
K
Trying to generate some basic sine waves with phaser
Asking for help
ARTIQ
Sinara
karps77
replied
17 Jan
2
2 replies
D
Switch to Vivado 2024?
Asking for help
Sinara
dtsevas
replied
16 Jan
5
5 replies
D
Upload device map to satellites?
Asking for help
ARTIQ
Sinara
occheung
replied
16 Jan
3
3 replies
D
Noise on Fastino output?
Asking for help
ARTIQ
Sinara
sb10q
replied
16 Jan
1
1 reply
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Sinara
Transfer values to master once and then access them from all kernel functions
EEPROM aliasing when using DRTIO
Number of packets before reply from satellite
Which SFP speeds for different Kasli & Kasli SoC versions?
Kasli SoC `aux packet error (link down)` and `DrtioError(LinkDown)`
Ramp Function with SUServo
Control Stabilizer from Kasli
Looking for stabilizer mezzanine with AD9910 (or similar) DDS
Inquiry about Bidirectional TTL in Output Mode
DRTIO satellite: Kasli SoC vs. Kasli?
Automated firmware building for the Kasli SoC
artiq-zynq compilation from December 2024 crashes?
How do I obtain Vivado build logs for my Kasli SoC firmware?
Confusing with example codes
Arbitrary keys in system description file?
(PHASER) Simulatenous signals beyond the +-10MHz range of DUC frequency
Trying to generate some basic sine waves with phaser
Switch to Vivado 2024?
Upload device map to satellites?
Noise on Fastino output?
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