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Sinara

External clocking setup causing crate to become unresponsive?
Fast TTL output control from a binary number
Urukul DDS synchronisation/PLL error lights on
Sampler device error
How to access Kasli's EEPROM (`LOC0`)
Does the Fastino need two EEM connectors?
Kasli 2.0 fan control
call to get_channel_att is erazing the existing attenuation values
Phaser board leds and RF issue
Artiq moninj connection issue
Dead time between build and run
Incorrect frequency output from phaser with trf_write() function
Time tag with TTL input
Urukul init() error "no valid window/delay"
unable to get DDS output.
Sweep a large range of frequencies in one experiment with Phaser board
Phase ambiguity in Urukul
Best method for retrieving dataset data while inside kernel
Integration of Sinara (ATRIQ) and other control system
Minimum input voltage for SMA TTL

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