Migen

F
Can not access to Vivado when building the ARTIQ
- Asking for helpARTIQMigen
- I recently changed our ARTIQ hardware config which added a zotino. And I would like to build my ARTIQ firmware to let my Kasli-SoC adapting to this change. But when I ran the ...
10 replies
F
reg dummy_x in generated verilog
- GeneralMigen
- Hi, What is the significance of the dummy_s and dummy_d registers in generated verilog code? Are those just delimiters for modules and their interfaces or is there something m...
1 reply
J
How do AD9914 moninj probes work?
- GeneralARTIQMigen
- Hello! We are trying to debug some problems we are having with our AD9914 DACs in a NIST_QC2 backplane seated in a KC705. DDSs aren't initializing reliably. Even if they do, w...
1 reply
A
Specifying clock domain for sub-module in a multi-clock parent module.
- Asking for helpMigen
- Hi, May I ask you how to specify which clock domain is used by a sub-module? For example, if in my parent module, I have two clock domains. I then create a sub-module, how can...
3 replies
A
How to reset a submodules from parent module
- Asking for helpMigen
- Hi, I am new to migen and trying something with it. I have a question about submodule. As far as I know, clock and reset signal is implicit defined for a module. If I use that...
2 replies
R
Repair Migen URL links
- GeneralMigen
- The Migen website has links to its tutorial and documentation that do not point the described resources. [Migen] (https://m-labs.hk/gateware/migen/). The bad links are: -https...
2 replies
F
Testbench not working
- Asking for helpMigen
- I have this code: #!/usr/bin/env python3 from migen import * class Test(Module): def __init__(self, clk): self.clock_domains.cd_clk = ClockDomain() self.comb += self.cd_clk.cl...
1 reply
F
2 clock domains in submodule?
- Asking for helpMigen
- I'm learning migen and implemented my first core, VgaOutputGenerator: https://pastebin.com/XC4kwgZq But I think I didn't really understand how to use multiple clocks in a subm...
0 replies
S
Always Reset Signals That Are Assigned Within An FSM
- Asking for helpMigen
- if a module assigns a value to a Signal within an finite state machine implemented as a migen.genlib.fsm.FSM, then generated Verilog will append an extra assignment to the alw...
1 reply
R
Simulating reset
- Asking for helpMigen
- How does one drive a sync statement's default reset signal and successfully simulate it using migen? I don't think the simulator supports it. Whereas I can set any other input...
3 replies
D
Accessing CSR from the host with Migen
- GeneralMigenMiSoC
- I came across an outdated hello world tutorial for Migen which really confuses me. In this tutorial, the author describes how CSRs (e.g. CSRStatus and CSRStorage) can be acces...
2 replies
C
Porting a New Board To Migen
- Giving a tutorialMigen
- In September 2017, I wrote a blog post that discusses how to seamlessly add a new FPGA development board to Migen. The idea is that porting a board to Migen is actually minima...
0 replies

Migen