ARTIQ

Clarifications regarding the ARTIQ release model and AFWS
- GeneralARTIQ
- ARTIQ follows a rolling release model, with beta, stable, and legacy channels. Different releases are saved as different branches on the M-Labs ARTIQ Git repository, and our s...
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ARTIQ-8 released
- AnnouncementsARTIQ
- ...uted DMA, as well as any future DRTIO improvements, can be used on EFC/Shuttler. Sinara Phaser should follow suit in a future ARTIQ version. Another major DRTIO improvement in...
0 replies
NAC3 - New ARTIQ Compiler 3: Prealpha release
- GeneralARTIQ
- I am pleased to announce the Prealpha release of NAC3, a new compiler for ARTIQ. It is a major, backward-incompatible rewrite which features improved compilation speeds, a muc...
4 replies
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Create a description file of SUServo
- Asking for helpARTIQSinara
- Hello, I am trying to exploit our ARTIQ SUServo feature to stablize our laser. However, our hardware was not set to SUServo mode when it had been ordered. Now, I know that the...
3 replies
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Alternative Python Execution Approach for Deterministic FPGA Applications?
- GeneralARTIQ
- Hi everyone, I’ve built a Python execution system that runs directly on a softcore processor implemented in FPGA logic. It’s not MicroPython or standard Python-on-Linux — it’s...
6 replies
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Kasli-SoC RPC Throughput Performance Comparison
- GeneralARTIQ
- We have recently observed performance improvements for certain RPC throughput tests on Kasli-SoC after upgrading the rustc and LLVM versions for the artiq-zynq firmware. The s...
0 replies
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artiq.db failed to download in MSYS2
- Asking for helpARTIQ
- Hello, we have installed MSYS2 using the offline installer provided in the ARTIQ manual. On Windows 10. The problems we have: Any command of the sort ''pacman -S ...'' returns...
3 replies
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How do users choose folder to save data in?
- GeneralARTIQ
- By default ARTIQ saves data in the "results" subfolder under the working directory that artiq_master is called at. Is there an argument that can be used to change the data sav...
9 replies
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ARTIQ 9 with NAC3 not providing error messages
- Asking for helpARTIQSinara
- I've flashed a crate with gateware built from the NAC3 branch of ARTIQ, and I have a nix environment with the same git version for running the master/dashboard/moninj/coreanal...
3 replies
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ARTIQ9/NAC3 gateware issue
- Asking for helpARTIQSinara
- I'm trying to test out ARTIQ9 with NAC3 on a spare Kasli crate we have, and I have the master/dashboard/moninj working and talking to the crate. I haven't been able to run any...
2 replies
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Reading values of the ADC input
- Asking for helpARTIQ
- Hi, when I'm trying to read an input voltage from an oscilloscope with an ADC channel it gives the following error: <artiq>/coredevice/sampler.py:149:13-149:16: error: the arg...
1 reply
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Problem encountered in setup nix develop environment
- Asking for helpARTIQSinara
- When we was running the followed code in my ubuntu system: nix develop git+https://git.m-labs.hk/m-labs/artiq-zynq\?ref=release-8 We met a problem in install phase: error: bui...
3 replies
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Difference of file size of the binary gateware and firmware
- Asking for helpARTIQSinara
- I currently setup a DRTIO system which contain two artiq machine, driven by different core --- Kasli and Kasli-SoC After I tried to build firmware and gateware for the Kasli a...
3 replies
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Flashing Shuttler
- Asking for helpARTIQ
- Hi all, We have a shuttler which we want to get up and running. As part of flashing the EFC (EEM FMC Carrier), we'd like to see the logs through the UART port. My understandin...
7 replies
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Bug in Urukul DRG: output depends on power cycling Kasli (SoC)
- Asking for helpARTIQSinara
- Again a bug that I managed to isolate well: I took the experiment from Bug in Urukul DRG: output amplitude is initialized to lower limit and added these lines just before the ...
1 reply
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Issue with sampler
- GeneralARTIQ
- I installed a new sampler ( v 2.3.1) with one EMM (port 0) in our system which has a master with a kasli soc and 3 satellites with kaslis. I rebuilt all the gateware and flash...
5 replies
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Bug in Urukul DRG: output amplitude is initialized to lower limit
- Asking for helpARTIQSinara
- I have isolated this bug extremely well. The self-contained experiment below writes an activated amplitude DRG into CFR2, sets DRCTL=high, waits 5 microseconds, then pulses io...
3 replies
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Trouble installing second dds (urukul ad9910)
- Asking for helpARTIQSinara
- Hello, I have been recently attempting to install a second dds (Creotech Urukul ad9910) into my labs Artiq system. Previous to the 2nd instillation there was already a functio...
14 replies
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Bug in new Urukul features
- Asking for helpARTIQSinara
- UPDATE: I leave this post here so it can be looked up, but I isolated constituent bugs better in these posts: https://forum.m-labs.hk/d/960-bug-in-urukul-drg-output-amplitude-...
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`proto_rev` in system description file required to use new Urukul features?
- Asking for helpARTIQSinara
- I tried to use the new Urukul features, but now a simple experiment that switches on a single DDS channel for 5 microseconds outputs a much much smaller voltage amplitude than...
3 replies

Clarifications regarding the ARTIQ release model and AFWS

ARTIQ-8 released

NAC3 - New ARTIQ Compiler 3: Prealpha release

Create a description file of SUServo

Alternative Python Execution Approach for Deterministic FPGA Applications?

Kasli-SoC RPC Throughput Performance Comparison

artiq.db failed to download in MSYS2

How do users choose folder to save data in?

ARTIQ 9 with NAC3 not providing error messages

ARTIQ9/NAC3 gateware issue

Reading values of the ADC input

Problem encountered in setup nix develop environment

Difference of file size of the binary gateware and firmware

Flashing Shuttler

Bug in Urukul DRG: output depends on power cycling Kasli (SoC)

Issue with sampler

Bug in Urukul DRG: output amplitude is initialized to lower limit

Trouble installing second dds (urukul ad9910)

Bug in new Urukul features

`proto_rev` in system description file required to use new Urukul features?